Description of new modules within eco32-30-port-14
0. Overview
This version of ECO32 starts working with the SPI bus. The bus
shares some lines with other devices (platform flash ROM, serial
flash ROM, and parallel flash ROM), which must be disabled in order
to avoid bus contention. The module "bio.v" (board-specific I/O)
does this under software control. It also provides ports for reading
the switches and lighting the LEDs. The module "spi.v" is responsible
for the actual SPI bus transfers. The SPI bus is shared between three
devices (DAC, ADC, and amplifier). As discussed on the mailing list,
the devices are accessed in a circle. One turn of the circle lasts
exactly as long as the inverse of the sampling rate for all SPI
devices. There is one SPI device already connected to the SPI bus
controller, the D/A converter. The module "fms.v" (FM synthesizer,
quite an exaggeration for now) sends samples to the D/A converter
via the SPI bus controller.
1. Module "bio.v"
With the "board I/O" module it is possible to read and write board
specific I/O devices (switches, LEDs). Also, the parallel flash ROM
can be disabled by setting a bit in a control register. Furthermore,
the module disables the other interfering ROMs (platform and serial
flash ROMs) permanently. Because there is no module for driving the
LCD display for the time being, this I/O device is also disabled
from here - but this may be changed in the future. It can be enabled
along with the SPI bus, because then the parallel flash ROM (which
interferes with the LCD display) is disabled.
1.1. Hardware Interface
The module has the usual bus interface, with a single address line
available within the module. There is one additional output from
this module, a signal named "spi_en", which can be set under software
control (see below). If the SPI bus should have control over the
shared lines, this signal must be 1; if it is 0, the shared signals
can be used by other devices. The external interface of the module
consists of connections to the switches, the LEDs, the LCD display,
and the enable lines of the ROMs.
1.2. Software Interface
The module presents a single 32-bit register at address 0xF1000000.
The register may be written, and can be read back at the same address.
The lowest 8 bits of the register drive the LEDs (1 meaning "on").
The most significant bit of this register is connected to the "spi_en"
output line. If reset, the SPI bus is inoperable, and the parallel
flash ROM can be accessed. If set, the SPI bus is operational, and
the parallel flash ROM is disabled. The module can also be accessed
at address 0xF1000004, but this is a read-only "register". The data
word read represents the state of the switches in the lowest 4 bits;
the other 28 bits are set to 0.
2. Module "spi.v"
This module implements the SPI bus controller. The SPI devices are
accessed periodically. The period, which is necessarily an integral
multiple of the sampling rate of any converter attached to the bus,
is determined by a counter. For the moment, the counter has 11 bits
and is clocked with the main system clock (50 MHz), with a resulting
sampling rate of 24.414 kHz. For every attached SPI device there is
an associated controller section within the module. It controls the
SPI bus during exactly those time slots that are alloted to the device.
For the time being, there is only a controller for the D/A converter
implemented.
2.1. Hardware Interface
The module does not have a system bus interface. It can be forced
to release all SPI bus lines by resetting the input "spi_en". Note
however, that the current access cycle is finished before the bus
is actually released, in order to properly finish sending commands
to the connected devices. Every device has an internal interface
to a module which generates values for or accepts values from the
device. Currently only the DAC has such an interface (description
see below). Every device also has an external interface (at least
a chip select line for the device). Additionally, the clock and
data lines for the SPI bus are driven by this module.
2.2. Software Interface
The SPI controller module does not have any registers which are
accessible by software.
3. Module "fms.v"
This module will eventually host an FM synthesizer. For the
moment, it consists of a single 32-bit register, which can
be written (and read back) by software. The upper 16 bits are
sent periodically to the "left" DAC (channel A), the lower
16 bits are sent periodically to the "right" DAC (channel B).
3.1. Hardware Interface
The module has the usual bus interface, with address lines
[11:2] available within the module for addressing registers
of the synthesizer. More interesting is the DAC controller
interface, which consists of a single input signal, "next",
and two 16-bit output signals, "sample_l" and "sample_r".
Every time the DAC controller needs a new sample, it reads
the two 16-bit signals ("left" and "right" samples in 16-bit
two's complement representation) and raises the "next" line
for one clock cycle (20 nsec). The value-generating circuit
(fms.v in this case) is expected to begin computation of
the next sample immediately. It must be finished until the
next time "next" gets active (which is 1/(24.414 kHz) =
40.96 usec later for the chosen sampling rate - but this
may be changed in the SPI module).
3.2. Software Interface
The module hosts a single 32-bit register at address 0xF0500000.
It can be read back at the same address, or at any other address
of the form 0xF0500zzz. The upper 16 bits go to the "left" channel
(A) of the DAC, the lower 16 bits go to the "right" channel (B).
Note however, that the DAC on our board is a 12-bit DAC. This
implies that the lower 4 bits on both channels are ignored.