Newsgroups: comp.cad.cadence,comp.sys.mentor,comp.lang.vhdl,comp.lang.verilog,comp.lsi,comp.cad.synthesis,comp.arch,comp.arch.fpga
From: jcooley@world.std.com (John Cooley)
Subject: INDUSTRY GADFLY: "From Beirut To Bosnia" + Reader Response
Organization: The E-mail Synopsys Users Group (ESNUG)
Date: Wed, 13 Mar 1996 21:05:47 GMT
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / INDUSTRY GADFLY: "From Beirut To Bosnia" & Response
_] [_
by John Cooley, EE Times Columnist
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
More than once I've thought of the Verilog/VHDL Wars as being the EDA
industry's equivalent of Beirut. What has made this war particularly
interesting to watch was the proxy propaganda war being fought via industry
analysts. Ron Collett of Collett International made big news for predicting
that VHDL was going to beat Verilog some time around '92. Gary Smith of
Dataquest also caused a minor uproar when he claimed at the '94 DAC that VHDL
revenues were just then beating Verilog revenues and projected it would only
get better for VHDL. Bill Fuchs, the never shy Chairman of Open Verilog
International (OVI), howled over the past four years that OVI's surveys
found that Verilog's revenues were easily *twice* to *four times* what these
analysts were seeing. Of course, just like Middle Eastern politics, each
side very quickly refuted the other side's industry numbers while quietly
accusing the other of being secretly affiliated with various VHDL or Verilog
terrorist organizations.
Suddenly, like UN Peacekeepers coming to Beirut on very large aircraft
carriers floating in the Mediterranean Sea, the industry association of
Electronic Design Automation Companies (EDAC) commissioned their own EDA
wide survey using the good offices of the Big Eight accounting firm Arthur
Anderson. The bombshell that came out of this study was that although for
the 1994 fiscal year EDAC found a revenue split of 54 per cent for Verilog
to 46 percent for VHDL on a total of $124 million -- for the first three
quarters (forth quarter numbers aren't out yet) of the 1995 fiscal year this
split has changed to 66 per cent for Verilog to 34 per cent
for VHDL on a total of $78 million! Doing his best CEO-speak,
Harvard MBA Alain Hanover (President & CEO of Viewlogic and Chairman of EDAC)
commented: "We needed objective statistics on topics like Verilog versus
VHDL, synthesis, and schematic capture to enable EDA companies to make
intelligent strategic business decisions. In 1995, we are also seeing a
clear lead in HDLs as the dominate input for design and Verilog as the
predominate language." (To get a copy of the EDAC Market Statistics report
covering this and much more call (408) 287-6371.)
A quick phone call to tell Bill Fuchs the news not only yielded a "Yeehaw!"
but also a litany of how frustrating it was for four years to be banging
heads with Dataquest and Collett International when his numbers so wildy
disagreed with theirs. "Now with EDAC's Arthur Anderson report, my numbers
are being vindicated. Verilog's won! I'm quite pleased!"
Privately I know this issue won't be completely resolved so quickly and
quietly. Like Beirut, it's a religious war. (I'm humorously wondering what
the VHDL Fundamentalists will do to undermine this heretical EDAC report.)
For 1996 I see the EDA industry's crisis-du-jour moving out of the Verilog
vs. VHDL Beirut and into a UNIX workstation vs. PC Bosnia. Just because EDA
products can run on PC's doesn't mean they can be PC priced. The economics
don't work. Yet engineers are genetically predisposed to "gak" at the idea
buying $70,000 worth of software to run on $1,500 worth of PC. To get a
better view of this new industry wide hot button I suggest that you come to
Richard Goering's panel at IVC on Weds., Feb 28th at the Santa Clara
Convention Center. It should be an eye opener.
-------
John Cooley runs the grassroots E-mail Synopsys Users Group (ESNUG), is
president of the Users Society of Electronic Design Automation (USE/DA), and
makes his living as an independent contract ASIC/FPGA designer. He loves
receiving e-mail from fellow engineers at "jcooley@world.std.com" or phone
(508) 429-4357. [ Copyright 1995 CMP/EE Times Publications ]
============================================================================
ONE READER'S RESPONSE (more are always welcome!)
From: Mahendra Jain, Executive Director, VHDL Int'l
Dear EE Times,
I'd like to respond to John Cooley's Industry Gadfly Column in last week's
issue. Once again, I believe his comments are based on incomplete
information. I hope you'll allow me to explain.
The VHDL/Verilog HDL wars are indeed over. We do not believe there are any
wars. The co-location of IVC/VIUF is a symbol that there's no war and, in
fact, shows that OVI and VHDL International are working together
cooperatively.
John Cooley's column discusses the preliminary HDL simulator revenues EDAC
released recently. We think the information provided by EDAC is incomplete
and premature. For example, we don't have information on number of units
sold or the average selling price per unit. We believe these are key
factors and would probably show a different set of results. Industry
research continues to show that designers are opting to use VHDL on a
worldwide basis. VITAL libraries are only now becoming available and over
the next three to six months more will be introduced to support deep
submicron design. VHDL International is publishing a table of available
VITAL Libraries in VHDL Times next month.
VHDL International isn't about comparing languages, simulators or revenues.
Our goal is to better serve the designer community by helping provide tools
to educate them, make their jobs easier and make them more productive. The
EDA Community has the responsibility to provide both VHDL- and Verilog
HDL-based tools as long as it is what designers want.
As the Executive Director of VHDL International, I am disappointed that the
language war continues to be fueled by a seemingly neutral and responsible
industry observer.
Best regards,
Mahendra Jain
Executive Director
VHDL International
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 4126 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
From: jcooley@world.std.com (John Cooley)
Subject: REPOST: "Rorschach Test 273 Engineers With The Verilog/VHDL Contest"
Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog,comp.cad.synthesis
Date: Mon, 17 Nov 1997 18:42:46 GMT
Organization: The E-mail Synopsys Users Group (ESNUG)
Path: lyra.csx.cam.ac.uk!server1.netnews.ja.net!rill.news.pipex.net!pipex!uunetukout!warm.news.pipex.net!pipex!join.news.pipex.net!pipex!uunetukin!nntprelay.mathworks.com!news-peer.gip.net!news.gsl.net!gip.net!cpk-news-hub1.bbnplanet.com!news.bbnplanet.com!newsfeed.internetmci.com!192.48.96.126!in2.uu.net!world!jcooley
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[ Apparently the perinnial Verilog vs. VHDL discussions have heated up
again in the hardware design newsgroups because I'm being "pelted"
again by people wanting copies of this and the preceeding article to
it. Rather than remailing it, I'm reposting it here. - John ]
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / RORSCHACH TESTING 273 ENGINEERS
_] [_ WITH THE VERILOG/VHDL CONTEST
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
In March '95, at the annual Synopsys Users Group meeting, a 90 minute ASIC
design contest was held. Using either Verilog or VHDL the 14 contestants
were to create a gate netlist for the fastest fully synchronous loadable
9-bit increment-by-3 decrement-by-5 up/down counter that generated even
parity, carry and borrow.
Of the 9 Verilog designers in the contest, only 1 didn't get to a final gate
level netlist because he tried to code a look-ahead parity generator. Of the
8 remaining, 3 had netlists that missed on functional test vectors leaving 5
Verilog designers who got fully functional gate-level designs. The surprize
was that, during the same time, *none* of 5 VHDL designers in the contest
managed to produce any gate level designs.
In the July issue of "Integrated System Design", I published a very detailed
write-up of the contest. As a sort of industry-wide Rorschach test, I asked
the readers to e-mail me their background, their vote for whether Verilog or
VHDL "won", and the open-ended question of why they thought the way they did.
Here's what 273 ASIC design engineers were thinking...
DEMOGRAPHICS A total of 317 letters were recieved but only 273 were counted;
88 VHDL-only, 76 Verilog-only, 66 bilinguals, and 43 unknown language users.
None of the following people's opinions were tabulated: 19 asking only for
the contest's test suites, 17 people employed by EDA vendors, 3 university
Computer Science types, a chemistry professor, an EE PhD candidate seeking
permission to translate the design contest into Estonian, 3 EDA sales
pitches and one "Christ is Coming Soon!" letter. Four ESDA vendors wrote
for the contest specs making great claims in the process but were never
heard from again after getting them.
PAYBACK TIME Because of all the time and energy some the EDA sales staffs
put into pushing VHDL onto engineers happy with Verilog, this contest seemed
to be a clarion call for Verilog customers (14 to be exact) to tell me the
shenannigans they suffered at the hands of these EDA vendors. Synopsys, Inc.
topped the perpetrator list because they had a Verilog/VHDL synthesis tool
but only a VHDL simulator (VSS) to go with it. Hence, their sales staff was
quite motivated to creatively work overtime promoting VHDL over Verilog.
> When I worked at HP Roseville, I remember taking my first Synopsys training
> class. The instructor from Synopsys kept telling us that we were making a
> grave mistake using Verilog and that EVERYONE who was anyone was using
> VHDL. (I actually was worried at the time we had chosen the wrong
> language, and that he was really unbiased. As I look back it is obvious
> that he was probably a VSS VHDL salesman and did Design Compiler training
> on the side.) I'm glad we chose Verilog, especially when teaching new
> engineers and when getting our SW/FW folks (who eat/sleep/breathe "C") to
> understand the HDL I have written. I would really encourage any new HDL
> designer to choose Verilog rather than VHDL, since it is much easier to
> learn, use and eventually master.
>
> - Scott C. Petler
> Next Level Communications, Inc.
I laughed out loud when I saw this next letter. At the Synopsys Users Group
meeting three years ago, the HP Boise Laserjet VHDL "success" story was a
main event. And recently, Synopsys even used it in a major ad campaign
promoting VHDL with synthesis in all the trade journals!
> I have spent most of my design life (last 4 years) working on VHDL designs.
> Recently, I have been forced into the Verilog camp by a vendor. My initial
> concerns that Verilog would not have the functionality that I needed have
> been proven wrong. Verilog does what I need better - and the simulators
> are faster than VHDL simulators.
>
> Since VHDL was driven mostly by the government which has no interest in the
> productivity of the designers, it is not surprising to see your results
> from the contest. VHDL syntax hinders progress and does not improve the
> robustness or quality of the design. The behavioral compilers, not VHDL,
> make the most sense for doing even more sophisticated design work.
>
> Please don't make be go back to VHDL!
>
> - Robert Rust
> Hewlett Packard Boise Printer Division
HOW TO NOT LIE WITH STATISTICS To my surprize, hardly anyone (2 VHDL-only
users) tried to say this was statistically insignificant, but 4 (5%) VHDL-
only, 5 (7%) Verilog-only, 3 (5%) bilinguals, 3 (18%) EDA vendors, and one
(25%) professor thought is was mathematically kosher.
> One question that you have the VHDL bigots make in this "trial" can be
> completely refuted: the results are statistically significant as the term
> is usually defined. To say a result is statistically significant, you
> show that it was very unlikely to be achieved by chance. Given: 9 Verilog
> designers and 5 VHDL designers, choose 8 winners at random. What is the
> chance that they will all be Verilog designers?
>
> Answer: (9/14)*(8/13)*(7/12)*(6/11)*(5/10)*(4/9)*(3/8)*(2/7)
> = 0.002997
> = 1/333.7
>
> So there is one chance in 333.7 that this result is purely by chance. We
> can't argue that this result isn't statistically significant given this
> figure. This is a greater than 99% confidence level. If we take one VHDL
> designer out (the one who suffered from the VHDL simulator bug), we get
> (9*8*...2)/(13*12*...6) or 1/143.
FROM THE FOUNDRY Rather than risk losing any business or possibly angering
customers, six ASIC foundry and three FPGA vendors wrote carefully balanced
replies that said effectively: "Whatever the customer wants is right." One
former foundry person wrote on condition of anonimity:
> In a previous life, I worked as an onsite applications engineer for an ASIC
> vendor. The customer that I supported was developing 17 ASIC's for a large
> program. The customer chose to develop some of the designs in VHDL and
> others in Verilog. All were synthesized using Synopsys. The smallest
> design was 15K gates, the largest was 100K gates. I interviewed the design
> teams to gather some interesting statistics. Conclusions were:
>
> 1) Designs done in Verilog were, without fail, completed faster than
> those done in VHDL. (In terms of gates/manweek.)
>
> 2) Adding designers to VHDL and Verilog based designs SLOWED the
> gates/manweek metric, but adding designers to VHDL-based designs
> had a greater negative impact. (Probably due to data-typing issues.)
>
> 3) Single or dual-person design teams out performed all others.
>
> The designers (80) were of various experience levels, working in groups of
> 2 to 10. From end of specification to final signoff, the highest
> performancing was a Verilog team at 1500 gates/manweek, the lowest was a
> VHDL team with 8 gates/manweek!
VHDL'S STRATEGIC RETREAT In the engineering press and on the Internet prior
to the Verilog/VHDL Design Contest, the VHDL bigots managed to create an
image that the only problem their language of choice had was in convincing
the ASIC foundries to provide VHDL libraries. Hence, the big media presence
of "VHDL Initiative Towards ASIC Libraries" (VITAL). With the Design Contest
results 39 (44%) VHDL-only, 4 (5%) Verilog-only, 19 (29%) bilinguals, and 14
(33%) unknown language users conceded that Verilog "wins" in low level gate
type designing, but VHDL "wins" in higher level abstract designing. That is,
VHDL is retreating from gate level design to "own" high level design. (Just
weeks before the Design Contest, VHDL proponents were openly claiming VHDL
was just as good at gate level ASIC design as Verilog was.)
> I've successfully used both languages, think that the results of the
> contest are directly correlated to the structure of the languages. It
> exactly mirror my experiences. Given this, I still prefer VHDL. My first
> design was with Verilog and on the first day (after I'd taken the Synopsys
> Verilog class) I was able to write useable code that was simulatable and
> synthesizable. I found the language relatively simple and easy to use, and
> thus easy to produce results with. When I changed jobs I started using
> VHDL and have produced several large chips with it. It took me more than a
> week to get my first VHDL code to compile, not to mention simulate. At
> first I couldn't stand VHDL, but as time went by I found that it's more
> structured, verbose and abstract from actual hardware. Although harder
> to learn and easier to mess up, it's valuable on large projects.
>
> - Sean Atsatt
> Seagate
TESTING MORE IMPORTANT For some engineers testing was more important than
other issues: 14 (16%) VHDL-only and 9 (12%) Verilog-only stated that their
chosen HDL was best for this; 9 (14%) bilinguals and 4 (9%) unknowns liked
VHDL on testing; 8 (12%) bilinguals and 1 unknown preferred Verilog.
> It's clear from the contest that Verilog can get you to a netlist faster
> than VHDL - period end of story. BUT my experience has shown that the
> amount of time to generate a netlist is small in comparison to the over
> all ASIC design schedule. Verification (i.e. test bench generation) makes
> up most of the ASIC design schedules I put together. Verilog's C-like
> structure provides a very flexiable environment which integrates very
> smoothly into most test bench solutions. In addition, focusing on test
> benchs illuminates one of Verilog's best features: the PLI. I don't
> believe VHDL provides a PLI counterpart. Without a PLI many of the
> third part tools that I rely on, such as Signalscan, would not be available.
> At GI we have made use of Verilog's PLI for many tasks ranging from memory
> efficient input stimulus handling to automated test vector generation.
>
> - Rick Price
> General Instrument Corp
EXPERIENCE QUESTIONS Quite a number of VHDL proponents raised the issue that
the VHDL contestants might not be experienced with the tools they had at hand
or in ASIC design itself. (No one questioned the experience of the Verilog
contestants because all but one got to gates.) The VHDL contestants used
Synopsys for synthesis and had a choice of Cadence and Synopsys for VHDL.
What follows are the sizes of all the ASIC's and FPGA's the VHDL contestants
have designed plus what EDA tools they've used.
TABLE 1) ASIC, FPGA & TOOL EXPERIENCE OF VHDL COMPETITORS
----------------------------------------------------------------------------
Ravi Srinivasan ASIC's: 60K, 115K partial ASIC's: 30K, 45K FPGA's: 0
Texas Instr. Tools: Synopsys VHDL & Design Compiler, Aida, Verilog-XL
Jan DeCalwe ASIC's: 60K, 22K, 65K, 35K, 83K FPGA's 3K, 6K, 4K, 2K
Easics, Ltd. Tools: Synopsys VHDL & Design Compiler, Actel P&R, Altera
MaxPlusII, Verilog-XL
Jeff Solomon ASIC's: 125K (schm.) partial 55K FPGA's: 2K, 6K, 10K
NASA Goddard Tools: Synopsys VHDL & Design Compiler, Concept/Valid,
Cadence LWB RapidSim, LSI CMDE
Prasad Paranjpe ASIC's: 17K, 20K, 50K, 30K partial ASIC's: >5 FPGA's: 0
LSI Logic Tools: Synopsys VHDL & Design Compiler, Vantage, LeapFrog,
Verilog-XL, IKOS, MTI, LSI CMDE
Vikram Shrivastava partial ASIC's: lots of synthesis/static timing/CMDE
LSI Logic Tools: Synopsys VHDL & Design Compiler, Verilog-XL, CMDE
---------------------------------------------------------------------------
The Verilog based contestants had similar tool and ASIC design experiance.
One noteable exception was Howard Landman of HaL Computers. In his 15 years
of CAD management experience Landman has never designed a single ASIC, yet,
using Verilog he managed to take third place in the design competition!
FAIRNESS: Of those 44 (16%) engineers who commented on fairness, 6 (2%)
(all VHDL-only's) felt the contest was "rigged" in Verilog's favor (because
they felt it was too low level) while the remaining 38 (14%) overall
designers saw it as honorable.
> Even before I read the "Closing Arguments to the Jury..." I was thinking
> that this design contest was perfect because it showed exactly what
> engineers are up against - tools are late, support is incomplete and/or
> inexact, workstations crash inexplicably, testing is incomplete, etc. The
> only thing missing was a change in the specification 10 minutes before the
> end of the contest. Cool contest - thanks for all the work.
>
> - Richard Schmidt
> Exabyte
Two engineers felt that Steve Golson should have won because his design met
the design spec while Larry's didn't -- but this error wasn't caught by the
faulty test suite.
> Steve Golson is the winner. Clearly stated in the spec: "11" - Q holds
> state. The inability of your testbench designers to adequately test the
> design should not be held against Steve (or should I say assist Larry).
> The bottom line must be that the design is functionally accurate.
>
> - Michael Fitzsimmons
> Motorola
TYPE WARS: The most controversial topic was whether strong typing is a good
thing or a bad thing. Some VHDL-proponents felt it was VHDL's core strength,
while other VHDL-proponents saw strong typing as an increadable annoyance!
Those who knew VHDL had very strong opinions on this. Of the bilinguals,
19 (29%) hated strong typing, 6 (9%) loved it, 6 (9%) noted it but couldn't
decide. Of the VHDL-onlys, the breakout was 13 (15%) hate, 17 (19%) love,
10 (11%) noted but couldn't decide. Of Verilog-onlys and unknowns, 7 (5%)
hated, 4 (3%) loved, 6 (4%) noted but couldn't decide.
> I thought the contest was a good one and I'm not seriously surprised by the
> results. I think the difference is in the nature of the languages,
> particularly the strong typing of VHDL, which at least one of your entrants
> had trouble with. VHDL forces you to think carefully about datatypes; if
> the design is simple logic, then this is a liability in terms of quick
> design time. VHDL has a better chance of producing a correct design if
> there is a mix of signal types, because you are forced to make sure they
> all convert correctly. C++ versus C is an analogy, the strong class
> binding of C++ objects can make for extra work up front making sure the
> types match up. In the long run, the design is more robust and easier to
> maintain because of it. I'm an IC designer who has used both - I'd use
> either one in real life, but I think verilog has the edge in quick draw
> contests.
>
> - Steve McChrystal
> Siemens Components Inc.
IOWA STATE UNIVERSITY It appears that the Design Contest's results have even
been verified by academia. What I liked about this unintentional validation
is that it's not 90 minutes. That is, there was all sorts of time for the
designers to do what they wanted. (I've recieved over 100 letters total
starting with: "Your results didn't surprize me one bit!" If they were from
the VHDL oriented I got explanations that VHDL tools took longer to run, VHDL
was more verbose, and needed more intial time to get results. If they were
from the Verilog oriented, I got explainations that Verilog was essentially
C with wires, registers, built in flexable HW data types, concurrency and "it
should naturally win.")
> Actually, an interesting look at VHDL vs. Verilog was accidentally done in
> our graduate level logic synthesis course. We recently got Synopsys Design
> Compiler, Synopsys VHDL and Cadence Verilog-XL. While The rest of the
> class did their projects in VHDL, my lab partner and I did ours in Verilog.
> (We learned Verilog on our own; unlike my VHDL classmates, we had no class
> lectures, no T/A help, no professoral help.)
>
> The results of this were overwhelmingly in favor of Verilog as a tool to
> teach HDLs. Our final project, a 7500 gate, 35nsec RISC processor was ~25
> pages of Verilog. The VHDL people all ended up rushing near the end to
> just make something which worked and could be synthesized. Several groups
> failed at this altogether! (Whereas our project grew so large in
> functionality, our only problem was finding a workstation which had enough
> memory to handle the synthesis of the top level design.)
>
> The general comments in talking to the other students was they spent a
> majority of their timing fighting VHDL/Synopsys. We spent a majority of
> our time doing design work, and optimization.
>
> - Jeff Echtenkamp
> Iowa State University
BILINGUAL JUDGEMENTS The opinions I value the most are those of the bi-
linguals because they know both sides of the story. Of the bilinguals, 39
(59%) personally preferred Verilog overall, 16 (24%) were HDL neutral,
6 (9%) personally preferred VHDL, and 5 (8%) didn't comment on this.
> My transition from VHDL to Verilog came about 2 years back when I worked
> on a design which was about 45K gates. I learned Verilog as the ASIC
> Vendor we worked with was only comfortable doing a final signoff in Verilog
> rather than VHDL. With the flavor of both the languages, here are my
> comments:
>
> 1) VHDL is a good structured HIGH level language but I feel Verilog is
> closer to actual hardware which is being designed.
>
> 2) As far as behavioral goes, I rank VHDL at par with Verilog, but when
> it comes to RTL, I consider Verilog has the edge over VHDL as far as
> the time to market ( i.e. meeting the design schedule is concerned.)
>
> As far as the contest goes, I think verilog has again proved the point.
> Yes, with VHDL you can achieve the same target but at the cost of design
> time and support. In the present industry, time to market a product is
> the key to success. If a particular market window is missed, the ASIC and
> the man-months spent on it are a sheer waste. I strongly feel that given
> the choice and the design time I would opt for Verilog.
>
> - Subhodip Ghosh
> Western Digital Corp.
DON'T SHOOT THE MESSENGER! I'd like to close with the observation that this
design contest wasn't designed to be a referendum on Verilog vs. VHDL, but
it accidently became this. I was swamped with e-mail from both the Verilog
*and* VHDL camps *both* saying that Verilog won in this contest. Judging the
contest overall 175 (64%) felt "Verilog won", 16 (6%) felt "VHDL won", 48
(18%) felt "inconclusive" and 36 (13%) never voted! Along party lines, 70
(92%) Verilog-onlys voted "Verilog won" and 39 (44%) VHDL-only's did either
an "inconclusive" or "no vote."
> I am in the defense industry, and therefore we went right to VHDL when we
> switched to designing ASICs using HDLs. I have never learned Verilog. I
> have always thought the extremely tight typing in VHDL caused a lot of
> inefficiencies, and my guess is that this had a major effect in the contest
> results. Your contest seemed very fair to me. I would call Verilog the
> obvious winner.
>
> - Jim Levie
> Northrop Grumman
Yes, quite a few VHDL-only EDA companies like Synopsys, Mentor, Zycad, IKOS,
Model Tech, and ViewLogic have suddenly been working to either buy or
develope Verilog products for their customers. I don't see them leaving the
VHDL business, though. In my own consulting practice I've just finished a
Verilog ASIC for one customer and am now writing VHDL training material for
another. For the next few years I feel being fully Verilog/VHDL bilingual,
just like most EDA companies, is the wave of the future.
- John Cooley
part-time EDA Consumer Advocate
full-time contract ASIC/FPGA designer
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3881 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."